Various techniques and architectural configurations have been explored to maximize the throughput of a computing platform. One way to increase computational performance is to increase the frequency of the clock cycle, thereby increasing the number of actions performed in any given time period. While effective at increasing throughput, increasing the frequency of the clock cycle is accompanied by a substantial increase in the power consumption of the computing system. Another way to increase computational performance is to increase the amount of parallelism supported by the architecture of the computing platform. One such method of parallel architecture is Instruction Level Parallelism (ILP), in which a single instruction stream is split over multiple and independent computational units. However, similar to the increased frequency of the clock-cycle, total power consumption increases with each additional parallel unit, decreasing the energy efficiency of the computing platform. Some techniques have been implemented to optimize the parallelization of various processing units, but have done so at the expense of increasing the area of the architecture and power consumption due to the complexity of the implementations and additional circuitry required. In fact, many conventional throughput optimization techniques do not consider energy efficient computation as a main target. Rather, conventional techniques mainly look to achieve the highest throughput out of a computing platform.
Other methods have been applied to reduce the power consumption of a system. A commonly applied technique is voltage scaling, in which the power supply voltage is lowered to reduce the amount of power consumption. However, with the decrease in voltage and frequency, throughput of the system goes down, decreasing the overall performance of the computing platform.
Other commonly used optimization strategies of hardware architecture consider either throughput maximization or power minimization as a primary goal, because one parameter is generally optimized at the direct cost of the other parameter.